深圳市汇创佳电子有限公司

HC2510C 




1 

HC2510C 

Features 
l Phase - Locked Loop Clock Distribution for 
Synchronous DRAM Applications 
l Supports PC - 100 and Meets “ PC100 SDRAM 
registered DIMM Specification Rev. 1.2 ” 
l Distributes One Clock Input to One Bank of Ten 
Outputs 
l No External RC Network Required 
l External Feedback (FBIN) Pin is Used to 
Synchronize the Outputs to the Clock Input 
l Separate Output Enable for Each Output Bank 
l Operates at 3.3 V V cc 
l 125 MHz Maximum Frequency 
l On - chip Series Damping Resistors 
l Support Spread Spectrum Clock(SSC) 
Synthesizers 
l ESD Pro tection Exceeds 3000 V per MIL - STD -
883, Method 3015 ; Exceeds 350 V Using 
Machine Model ( C = 200 pF, R = 0 ) 
l Latch - Up Performance Exceeds 400 mA per